TLC320AD56 datasheet(33/42 Pages) TI1

33 / 42 page

4–7

4.3.10

Power-Supply Rejection (see Note 10)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VDD1

Supply-voltage rejection ratio, ADC channel,

DVDD

fi = 0 to 30 kHz

VDD2

Supply-voltage rejection ratio, DAC channel,

DVDD

fi = 0 to 30 kHz

VDD3

Supply-voltage rejection ratio, ADC channel,

AVDD

fi = 0 to 30 kHz

VDD4

Supply-voltage rejection ratio, DAC channel,

Single ended,

fi = 0 to 30 kHz

VDD4

AVDD

Differential,

fi = 0 to 30 kHz

† All typical values are at 25

°C.

NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV

peak-to-peak signal applied to the appropriate supply.

4.3.11

Timing Requirements (see Figure 3–1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td1

Delay time, SCLK

↑ to FS↓

td2

Delay time, SCLK

↑ to DOUT valid

tsu

DIN setup time before SCLK low

DIN hold time after SCLK high

CL = 20 pF

ten

Enable time, FS

↓ to DOUT valid

tdis

Disable time, FS

↑ to DOUT Hi-Z

td3

Delay time, MCLK

↓ to SCLK↑

twH

Pulse duration, MCLK high

twL

Pulse duration, MCLK low

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