DGG OR DL PACKAGE

(TOP VIEW)

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OEA

OEB1

2B3

GND

2B2

2B1

A1

A2

A3

GND

A4

A5

A6

A7

A8

A9

GND

A10

A11

A12

1B1

1B2

GND

1B3

NC

SEL

OEB2

CLKENA2

2B4

GND

2B5

2B6

2B7

2B8

2B9

GND

2B10

2B11

2B12

1B12

1B11

1B10

GND

1B9

1B8

1B7

1B6

1B5

GND

1B4

CLKENA1

CLK

NC − No internal connection

SN74ALVC16269

12BIT TO 24BIT REGISTERED BUS TRANSCEIVER

WITH 3STATE OUTPUTS

SCAS417B − OCTOBER 1993 − REVISED JULY 1995

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

CMOS) Submicron Process

Widebus

 Family

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Per JEDEC Standard JESD-17

the Need for External Pullup/ Pulldown

Resistors

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

description

The SN74ALVC16269 is a 12-bit to 24-bit

registered bus transceiver, which is intended

for applications where two separate ports

must be multiplexed onto, or demultiplexed

from, a single port. The device is particularly

suitable as an interface between synchronous

DRAMs and high-speed microprocessors. The

SN74ALVC16269 is designed specifically for

Data is stored in the internal B-port registers on

the low-to-high transition of the clock (CLK) input

when the appropriate clock-enable (CLKENA)

inputs are low. Proper control of these inputs

allows two sequential 12-bit words to be

presented as a 24-bit word on the B port. For data

transfer in the B-to-A direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data

for the A outputs. The register on the A output permits the fastest possible data transfer, thus extending the

period that the data is valid on the bus. The control terminals are registered so that all transactions are

synchronous with CLK. Data flow is controlled by the active-low output enables (OEA, OEB1, OEB2).

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVC16269 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)

packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the

same printed-circuit-board area.

The SN74ALVC16269 is characterized for operation from − 40

°C to 85°C.

Copyright

 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.