ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

15

POST OFFICE BOX 1443

test measurement

The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are

used to verify timing parameters of the TNETE110A output signals.

(c) FIREF TEST CIRCUIT

(b) AXMTP AND AXMTN TEST LOAD (AC TESTING)

(a) TTL OUTPUT TEST LOAD

180

Ω

FIREF

AXMTN

AXMTP

Test Point

CL

IOH

VLOAD

IOL

Point

Test

Test

Under

Output

TTL

50

Ω

78

Ω

50

Ω

X1

X1–Fil–Mag 23Z90(1:1)

(d) FXMTP AND FXMTN TEST LOAD (AC TESTING)

FXMTN

FXMTP

Test Point

50

Ω

50

Ω

X2

X2–Fil–Mag 23Z128(1:

√2)

25

Ω

25

Ω

FXMTN

FXMTP

Test Point

50

Ω

50

Ω

50

Ω

(e) FXMTP and FXMTN TEST LOAD (DC TESTING)

Test Point

50

Ω

Where: IOL

= Refer to IOL in recommended operating conditions

IOH

= Refer to IOH in recommended operating conditions

VLOAD

= 1.5 V, typical dc-level verification or

0.7 V, typical timing verification

CL

= 18 pF, typical load-circuit capacitance

Figure 3. Test and Load Circuit