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TNETA1585PGF bảng dữ liệu(PDF) 27 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
PDF  32 Pages
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TNETA1585PGF bảng dữ liệu(HTML) 27 Page - Texas Instruments

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TNETA1585
ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE
WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES
SDNS041A – NOVEMBER 1996 – REVISED JULY 1998
27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements (see Figure 10)
coprocessor interface (TCCX)
NO.
MIN
MAX
UNIT
1
tsu(TCCX)
Setup time, TCCX high before CLOCK
↑
10
ns
2
th(TCCX)
Hold time, TCCX valid after CLOCK
↑
1
ns
CLOCK
(input)
1
2
TCCX
(input)
Frame
Send
ACK
Scheduler
Source
Cell Type (3 bits)
CLP
DMA Number
(11 Bits)
Figure 10. TCCX Interface
timing requirements (see Figure 11)
coprocessor interface (RCCX)
NO.
MIN
MAX
UNIT
1
tsu(RCCX)
Setup time, RCCX high before CLOCK
↑
10
ns
2
th(RCCX)
Hold time, RCCX valid after CLOCK
↑
1
ns
RCCX
(input)
CLOCK
(input)
1
2
Frame
GCI
DMA Number (11 bits)
Figure 11. RCCX Interface
timing requirements (see Figure 12)
coprocessor interface (DAX)
NO.
MIN
MAX
UNIT
1
tsu(DAX)
Setup time, DAX high before CLOCK
↑
10
ns
2
th(DAX)
Hold time, DAX valid after CLOCK
↑
1
ns
DAX
(input)
CLOCK
(input)
1
2
Frame
DAV
DMA Number (11 bits)
Figure 12. DAX Interface



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