TPS75201MEP

FAST TRANSIENT RESPONSE 2A LOW DROPOUT VOLTAGE REGULATOR

WITH RESET

SGLS325 − JANUARY 2006

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

EN

5

I

Enable

FB/SENSE

7

I

Feedback input voltage for adjustable device (sense input for fixed-voltage option)

GND

17

Regulator ground

GND/HEATSINK

1, 10, 11, 20

Ground/heat sink

IN

3, 4

I

Input voltage

NC

2, 12, 13, 14,

15, 16, 18, 19

No connection

OUTPUT

8, 9

O

Regulated output voltage

RESET

6

O

Reset

RESET timing diagram

VI

Vres

(see Note A)

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

100-ms

Delay

100-ms

Delay

Output

Undefined

Output

Undefined

VIT + (see Note B)

VIT − (see Note B)

VIT − (see Note B)

VIT + (see Note B)

Less Than 5% of the

Output Voltage

NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

B. VIT − Trip voltage typically is 5% lower than the output voltage (95% VO) VIT− to VIT+ is the hysteresis voltage.