SST49LF004A datasheet(3/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

FIGURE 1: SINGLE-BYTE READ WAVEFORMS

TABLE

1: FWH READ CYCLE

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]1

FWH[3:0]

Direction

Comments

START

1101

FWH4 must be active (low) for the part to respond. Only the

last start field (before FWH4 transitioning high) should be

recognized. The START field contents indicate a FWH

memory read cycle.

IDSEL

0000 to 1111

Indicates which FWH device should respond. If the to IDSEL (ID

select) field matches the value ID[3:0], then that particular device

will respond to the whole bus cycle.

3-9

IMADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

IMSIZE

0000 (1 byte)

A field of this size indicates how many bytes will be or trans-

ferred during multi-byte operations. The SST49LF00xA will

only support single-byte operation. IMSIZE=0000b

TAR0

1111

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

then float to all ‘1’s and then floats the bus, prior to the next

clock cycle. This is the first part of the bus “turnaround

cycle.”

TAR1

1111 (float)

Float

then OUT

The SST49LF00xA takes control of the bus during this

cycle. During the next clock cycle, it will be driving “sync

data.”

RSYNC

0000 (READY)

OUT

During this clock cycle, the FWH will generate a “ready-

sync” (RSYNC) indicating that the least-significant nibble of

the least-significant byte will be available during the next

clock cycle.

DATA

YYYY

OUT

YYYY is the least-significant nibble of the least-significant

data byte.

DATA

YYYY

OUT

YYYY is the most-significant nibble of the least-significant

data byte.

TAR0

1111

OUT

then Float

In this clock cycle, the SST49LF00xA has driven the bus to

all ones and then floats the bus prior to the next clock cycle.

This is the first part of the bus “turnaround cycle.”

TAR1

1111 (float)

Float then

The master (Intel ICH) resumes control of the bus during

this cycle.

T1.3 504

1. Field contents are valid on the rising edge of the present clock cycle.

CLK

FWH4

FWH[3:0]

504 ILL F59.1

STR

TAR

RSYNC

IMS

IMADDR

IDS

DATA

TAR

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