SST45LF010 datasheet(2/14 Pages) SST

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Data Sheet

1 Megabit Serial Flash

SST45LF010

S71128-03-000

4/01

372

Reset

Reset will terminate any operation, e.g., Read, Erase and

Program, in progress. It is activated by a high to low tran-

sition on the RST# pin. The device will remain in reset

condition as long as RST# is low. Minimum reset time is

10 µs. See Figure 14 for reset timing diagram. RST# is

internally pulled-up and could remain unconnected dur-

ing normal operation. After reset, the device is in standby

mode, a high to low transition on CE# is required to start

the next operation.

An internal power-on reset circuit protects against acci-

dental data writes. Applying a logic level low to RST# dur-

ing the power-on process then changing to a logic level

high when VDD has reached the correct voltage level will

provide additional protection against accidental writes

during power on.

Read SST ID/Read Device ID

The Read SST ID and Read Device ID operations read the

JEDEC assigned manufacturer identification and the manu-

facturer assigned device identification IDs. These IDs may be

used to determine the actual device resident in the system.

Write Protect

The WP# pin provides inadvertent write protection. The

WP# pin must be held high for any Erase or Program oper-

ation. The WP# pin is “Don’t Care” for all other operations.

In typical use, the WP# pin is connected to VSS with a stan-

dard pull-down resistor. WP# is then driven high whenever

an Erase or Program operation is required. If the WP# pin

is tied to VDD with a pull-up resistor, then all operations may

occur and the write protection feature is disabled. The WP#

pin has an internal pull-up and could remain unconnected

when not used.

TABLE

1: PRODUCT IDENTIFICATION

Byte

Data

Manufacturer’s ID

0000H

BFH

Device ID

0001H

42H

T1.2 372

372 ILL B1.4

I/O Buffers

and

Data Latches

SuperFlash

Memory

X - Decoder

Control Logic

Address

Buffers

and

Latches

CE#

Y - Decoder

SCK

WP#

RST#

Serial Interface

FUNCTIONAL BLOCK DIAGRAM

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