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SST29SF040 bảng dữ liệu(PDF) 14 Page - Silicon Storage Technology, Inc |
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SST29SF040 bảng dữ liệu(HTML) 14 Page - Silicon Storage Technology, Inc |
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14 / 24 page ![]() 14 Preliminary Specifications 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Small-Sector Flash SST29SF512 / SST29SF010 / SST29SF020 / SST29SF040 SST29VF512 / SST29VF010 / SST29VF020 / SST29VF040 ©2001 Silicon Storage Technology, Inc. S71160-05-000 5/01 505 FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM FIGURE 11: SOFTWARE ID ENTRY AND READ 505 ILL F17.2 ADDRESS AMS-0 DQ7-0 WE# SW0 SW1 SW2 SW3 SW4 SW5 555 2AA 2AA 555 555 55 10 55 AA 80 AA 555 OE# CE# SIX-BYTE CODE FOR CHIP-ERASE TSCE TWP Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 11) Note: AMS = Most Significant Address AMS = A15 for SST29SF/VF512, A16 for SST29SF/VF010, A17 for SST29SF/VF020 and A18 for SST29SF/VF040 505 ILL F08.2 ADDRESS A14-0 DQ7-0 WE# Note: Device ID = 20H for SST29SF512, 22H for SST29SF010, 24H for SST29SF020, 13H for SST29SF040 21H for SST29VF512, 23H for SST29VF010, 25H for SST29VF020, 14H for SST29VF040 SW1 SW0 SW2 Device ID 555 2AA 555 0000 0001 OE# CE# Three-Byte Sequence for Software ID Entry TWP TWPH TAA BF 55 AA 90 TIDA |
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