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TPD4S1394DQLR bảng dữ liệu(PDF) 3 Page - Texas Instruments

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tên linh kiện TPD4S1394DQLR
Giải thích chi tiết về linh kiện  FIREWIRE ESD CLAMP WITH LIVE-INSERTION DETECTION CIRCUIT
PDF  10 Pages
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TPD4S1394DQLR bảng dữ liệu(HTML) 3 Page - Texas Instruments

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0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Voltage Bias (V)
TPD4S1394
www.ti.com
SLVSA55 – NOVEMBER 2009
ELECTRICAL CHARACTERISTICS
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage at D1+, D1-, D2+, and D2- to trip the
2.9
3.4
4.0
FWPWR_EN from high to low
Vdx
V
Voltage to trip the FWPWR_EN from low to high
2.7
3.2
3.8
VCLMP
Value on pin
No connect
2.45
V
Loading on FWPWR_EN = 50
ttrip
Time for FWPWR_EN to go low
0.5
2
5
μs
pF
treset
Time delay for the FWPWR_EN to go high after
FWPWR_EN = VCC
300
450
600
ms
trip condition is met
VBR
Breakdown voltage at VCLAMP
II = 1 mA
4.2
V
VD
Diode forward voltage for lower clamp
ID = 8 mA lower clamp diode
–0.6
–0.8
–0.95
V
FWPWR_E
Switch output
VCC
V
N
Dynamic resistance (for in and out clamp) of the
RDYN
I = 1 A
1
Ω
D+, D-
CIO
IO Capacitance of D+, D-
VIO = 2.5 V
1.5
2
pF
VCC = 3.3 V, FWPWR_EN =
ICC
Current Consumption
130
200
μA
high
(1)
A 0.1-
μF decoupling capacitor is required at VCC (pin 1).
TYPICAL CHARACTERISTICS
Figure 1. IO Capacitance vs IO Voltage (D+, D– Pins)
Copyright © 2009, Texas Instruments Incorporated
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