XIO2221 datasheet(95/196 Pages) TI1

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XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

5.4

Uncorrectable Error Mask Register

The uncorrectable error mask register controls the reporting of individual errors as they occur. When a

mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the

header log is not loaded, and the first error pointer is not updated. See Table 5-3 for a complete

description of the register contents.

PCIe extended register offset: 108h

Read only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5-3. Uncorrectable Error Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:21

RSVD

Reserved. Returns 000 0000 0000b when read.

20(1)

UR_ERROR_MASK

Unsupported request error mask

0 = Error condition is unmasked (default)..

1 = Error condition is masked.

19(1)

ECRC_ERROR_MASK

Extended CRC error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

18(1)

MAL_TLP_MASK

Malformed TLP mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

17(1)

RX_OVERFLOW_MASK

Receiver overflow mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

16(1)

UNXP_CPL_MASK

Unexpected completion mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

15(1)

CPL_ABORT_MASK

Completer abort mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

14(1)

CPL_TIMEOUT_MASK

Completion time-out mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

13(1)

FC_ERROR_MASK

Flow control error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

12(1)

PSN_TLP_MASK

Poisoned TLP mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

11:5

RSVD

Reserved. Returns 000 0000b when read.

4(1)

DLL_ERROR_MASK

Data link protocol error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

3:0

RSVD

Reserved. Returns 0h when read.

(1)

These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

PCIe Extended Configuration Space

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