VSP01M02 datasheet(39/91 Pages) TI1

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Monitor Signal

TGSection

High-Speed

SignalGenerator

015h-018h

SHP

SHD

AFESection

Delay

Controller

003h[1:0]

Sampling

Circuit

3-nsDelay

Signal

Selector

TPP

TPD

HIGH-SPEED PULSE ADJUSTMENT

VSP01M01

VSP01M02

www.ti.com .................................................................................................................................................................................................. SBES016 – MARCH 2009

The test pin (TPP, TPD) is set up by address 001h, data bit [3] = 1, as shown in Table 27. Table 28 describes

TPP and TPD.

Table 27. Monitor Pin Enable Register(1)

PARAMETER

VALUE

Monitor pin

001h[3]

1 = Enable

(1)

Refer to the Configuration Register section for details.

Table 28. Test Pin Output Select

TPP

TPD

1000b (8)

SHP

SHD

1001b (9)

CLPOB

CLPDM

1010b (10)

PBLK

HDIV

1011b (11)

HBLK

—

SHP and SHD are monitored at the TG section output, as shown in Figure 30. The actual sampling point is

delayed from the monitor point. The delay time is shown in Figure 30. The actual sampling point delay = delay

controller value (003h[1:0] = 0 ns-6 ns) + sampling delay (3 ns).

Figure 30. SHP/SHD Monitor Out

The high-speed pulse can be adjusted in steps of one pixel clock cycle per 100. The assignment register for

each pulse is shown in Table 29. The rising edge of the RG pulse as a reference.

Table 29. High-Speed Pulse Adjustment Register

CONTROL ITEM

TERMINAL NAME

FALLING

RISING

DELAY

014h[4:0]

—

G1Ah

G1h

G1Bh

011h[4:0]

010h[4:0]

—

G2Ah

G2h

012h[4:0]

013h[4:0]

G2Bh

SHP

015h[4:0]

016h[4:0]

SHD

017h[4:0]

018h[4:0]

003h[1:0]

019h[5:0]

ADCCK

—

019h[6]

Data out

B0-B15

—

002h[1:0]

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