SN74ACT2440

NuBus

™ INTERFACE CONTROLLER

SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991

POST OFFICE BOX 655303

9

slave read/write cycles

The ’ACT2440 provides all the handshake signals required to facilitate a simple NuBus

™ slave interface. In slave

applications, the local board is either written to or read from. When a NuBus

™ master wishes to access the local

board as a slave, it places the slave’s address on the bus during the start cycle. This action requires a compare

function to identify when the NuBus

™ address matches the 4-bit ID code associated with the local board. This

function is provided in the ’BCT2420 or can be built using standard MSI comparator functions. The controller

receives this input through the ID equal input (IDEQ).

Figure 8 shows the timing diagram of a typical slave read cycle. Figure 9 shows the timing diagram for a typical

slave write cycle. The slave external request status output (SEREQ) signals that the local board is being

accessed by another master. When the local board is ready to receive data and/or address information, it drives

slave grant access (SGNTA) active (low). When the local board is ready to respond to a read or write request,

it drives local acknowledge (LACK) low. The controller then issues an acknowledge on the bus, which completes

the transaction. Data and/or address information is enabled onto the local board as long as SGNTA is held low.

SEREQ does not go inactive until the first sample edge after SGNTA goes inactive. Data and/or address

information is disabled on the first sample edge after SGNTA returns inactive (high).

All slave external requests must be responded to with a local acknowledge. Allowing the NuBus

™ to timeout

does not reset the slave state machine.

higher performance slave cycles

Slave grant access (SGNTA) and local acknowledge (LACK) control the duration of slave cycles on the

’ACT2440. The simplest implementation, as previously explained, uses SEREQ, SGNTA, and LACK to form a

simple handshake. Faster slave cycles are possible by taking SGNTA low before the first sample edge after

START as shown in Figure 10. This mode of operation enables address and data information onto the local

board on the first sample edge after START. (Note: In slave-only applications, address information can be

enabled onto the local board sooner by tying AEN low on the ’BCT2440s.) As previously described, LACK

controls the completion of the slave cycle. Address and data information remains enabled onto the local board

until SGNTA returns inactive.

If the local acknowledge (LACK) and slave grant access (SGNTA) inputs are taken low before the first sample

edge after START, the acknowledge output (ACK) is generated on the next driving clock edge. This mode of

operation offers the highest performance but places the greatest demand on local circuitry.

slave lock detection

NuBus

™ locked (NLOCK) is a special output provided on the ’ACT2440 that signals when the local board is

being accessed by another master and an attention lock cycle has occurred. NLOCK informs the local board

not to modify any of its local resources until an attention null cycle is received. Figure 11 shows the timing

diagram for a slave lock-detection cycle. As shown in Figure 11, NLOCK goes active (high) when an attention

lock cycle occurs on the bus and the local board is being requested by another master. NLOCK will remain high

until the attention null cycle is received.

master block-transfer cycles

NuBus

™ 1987 master block transfers are supported by the ’ACT2440. Figure 12 shows the timing diagram for

a typical master block read. Figure 13 shows the timing diagram for a typical master block write.

A master block transfer consists of a start cycle, multiple data cycles to or from sequential address locations,

and an acknowledge cycle. The master controls the number of data words transferred and communicates this

information to the slave during the start cycle via address lines AD5–AD2. Table 2 shows the input code for

master block-transfer cycles.

During master block transfers, the slave acknowledges intermediate data cycles via the TM0 line. The ’ACT2440

detects these intermediate data cycles and generates the proper buffer control signals. The final data cycle from

the responding slave is a standard acknowledge cycle.