TL75LPxxQ SERIES

TL75LPxxY SERIES

LOW DROPOUT VOLTAGE REGULATORS

SLVS073A − SEPTEMBER 1992 − REVISED AUGUST 1995

3−2

POST OFFICE BOX 655303

POST OFFICE BOX 1443

functional block diagram

INPUT

Current

Limiting

Enable

ENABLE

Bandgap

OUTPUT

Overvoltage/

Thermal

Shutdown

GND/HEAT SINK

+

−

28 V

TL75LPxxY chip information

This chip, when properly assembled, displays characteristics similar to the TL75LPxx. Thermal compression

or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can be mounted with

conductive epoxy or a gold-silicon preform.

(1)

(5)

(4)

TL75LPxxY

(3)

(6)

(2)

OUTPUT

OUTPUT

SENSE

SIGNAL

GND

POWER

GND

ENABLE

INPUT

CHIP THICKNESS: 11 MILS TYPICAL

BONDING PADS: 7 X 7 MILS MINIMUM

TJ max = 150°C

TOLERANCES ARE

±10%.

ALL DIMENSIONS ARE IN MILS.

NOTE A. NOTE: SIGNAL GND and POWER

GND must be tied together as close to

device as possible. OUTPUT and

OUTPUT

SENSE

should

be

tied

together.

92

123

BONDING PAD ASSIGNMENTS

(1)

(5)

(3)

(6)

(2)

(4)