GRAYCHIP, INC.

- 4 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

following clock edge. The enables are designed to be used with the data valid strobes from the GC3011

digital resampler and GC2011 digital filter chips.

2.4

INPUT FORMAT

The input format circuit accepts complex data at the clock rate of the chip, or real data at twice the

clock rate of the chip. The input format circuit outputs pairs of samples to the mixer circuit where the pair is

either a complex data pair, or an even and odd time sample pair. A block diagram of the input circuit is

shown in Figure 2.

Figure 2. INPUT FORMAT CIRCUIT

The data, clock and sync operate at a rate which is twice the chip’s clock rate in the high speed

mode. The differential receivers convert the PECL signals to CMOS voltage swings. The data splitter divides

the high speed data stream into two streams at half the high speed rate. One stream contains the odd time

samples and the other contains the even time samples. The high speed sync synchronizes the data splitter

by identifying a sample which should show up in the even data stream. The data splitter circuit divides the

high speed clock in half and outputs it as HCKO. The HCKO clock should be buffered and used as the clock

input to the chip (See Section 2.3). The HSO sync is the high speed sync reclocked by HCKO. The HSO

sync is used within the chip as one of the synchronization sources for the internal circuitry, or can be routed

HCK

HCK

HSI

HSI

HS

DATA

(12 bits)

External Clock Driver

TO CHIP

CLOCK

HCKO

DATA

SPLITTER

DATA

MUX

Diagnostic

Ramp

Data

To

Mixer

To Internal

+

-

+

-

+

-

COMPLEX

DATA

I

Q

Even Odd

Mode

Select

Receiver Enable

and Termination Enable

XI

XQ

12 Bits

12 Bits

12 Bits

12 Bits

12 Bits

12 Bits

VTERM

clock

sync

data

sync

out

clock

out

Sync Generator

and Counter

HSO