Appendix B: Jitter Characteristics in Input Clock Mode

0

20

40

60

80

100

120

140

160

-

-

-

-

-

-

-

-

10

100

1k

10k

100k

1M

10M

100M

Single-SidebandFrequency(Hz)

CDCE421A

If the CDCE421A is being referenced by an external and cleaner LVCMOS input of 35.42 MHz and 33.33 MHz,

respectively, Figure 9 and Table 13 show the SSB phase noise plot and phase noise data of the output at 708

MHz for LVPECL from 100 Hz to 40 MHz from the carrier.

Figure 9. SSB Phase Noise at 708-MHz LVPECL Output with LVCMOS Input of 35.42 MHz

PARAMETER

MIN

TYP

MAX

UNIT

phn100

Phase noise at 100 Hz

–95

dBc/Hz

phn1k

Phase noise at 1 kHz

–105

dBc/Hz

phn10k

Phase noise at 10 kHz

–109

dBc/Hz

phn100k

Phase noise at 100 kHz

–114

dBc/Hz

phn1M

Phase noise at 1 MHz

–126

dBc/Hz

phn10M

Phase noise at 10 MHz

–146

dBc/Hz

phn20M

Phase noise at 20 MHz

–146

dBc/Hz

JRMS

RMS jitter from 10 kHz to 20 MHz

438

fs

(1)

Phase noise specifications under following assumptions: input frequency = 35.42 MHz (VCO = 2, prescaler = 3, output divider = 1),

output frequency = 708 MHz at LVPECL.

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