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33813 bảng dữ liệu(PDF) 43 Page - Freescale Semiconductor, Inc |
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33813 bảng dữ liệu(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 54 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 43 33813 Table 21 defines the commands and default state of the internal registers at POR. SPI commands may be sent to the device at any time while the device is in the Normal state. Messages sent are acted upon on the rising edge of the CSB input. Bit value returned equals bit value sent for this command 5.3.10 SPI Commands There are seven SPI commands that can be issued by the MCU to: • Do a SPI Check verification • Read the contents of the SPI configuration registers • Write the contents of the SPI configuration registers • Read the contents of the SPI status registers • Write the contents of the SPI status registers • Read the contents of the SPI control registers • Write the contents of the SPI control registers 5.3.10.1 SPI Registers The SPI interface consists of a block of four 8-bit read/write registers. There are three types of SPI registers: • Configuration Registers - These registers allow the MCU to configure the various parameters and options for the various functional blocks. • Control Registers - These registers are used to command the outputs on and off and set the PWM duty cycle values. • Status Registers - These registers report back faults and other conditions of the various functional blocks. The following acronyms are use in the SPI table: • OC = over-current, could be short to battery (SB) • OV = over-voltage • OT = over-temperature • OL = open load • SG = short to ground • PWM = pulse width modulation Table 21. SPI Command Messages Command Control Address Bits Data Bits hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI Check 0 0 0 0 0 X* X* X* X* X* X* X* X* X* X* X* X* Read Configuration Register 1 0 0 0 1 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Write Configuration Register 2 0 0 1 0 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Read Status Register 3 0 0 1 1 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Write Status Register 4 0 1 0 0 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Read Control Register 5 0 1 0 1 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Write Control Register 6 0 1 1 0 <0000> Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 SPI Check Response 7 0 1 1 1 X* X* X* X* X* X* X* X* X* X* X* X* |
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