SL74HC75 datasheet(4/5 Pages) SLS

4 / 5 page

SL74HC75

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS(C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tPLH, tPHL

Maximum Propagation Delay, D to Q (Figures 1

and 5)

2.0

4.5

6.0

125

155

190

tPLH, tPHL

Maximum Propagation Delay , D to Q

(Figures 1 and 5)

2.0

4.5

6.0

110

140

165

tPLH, tPHL

Maximum Propagation Delay ,Latch Enable to Q

(Figures 2 and 5)

2.0

4.5

6.0

145

180

220

tPLH, tPHL

Maximum Propagation Delay ,Latch Enable to Q

(Figures 2 and 5)

2.0

4.5

6.0

125

155

190

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 3 and 5)

2.0

4.5

6.0

110

CIN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Latch)

Typical @25

°C,V

CC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption:

PD=CPDVCC

2f+I

CCVCC

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time,

Input D to Latch Enable

(Figure 4)

2.0

4.5

6.0

100

125

150

Minimum Hold Time,Latch

Enable to D (Figure 4)

2.0

4.5

6.0

Minimum Pulse Width, Latch

Enable Input

(Figure 2)

2.0

4.5

6.0

100

120

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

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