AM1802 datasheet(96/180 Pages) TI1

96 / 180 page

AM1802

SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012

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Figure 5-22 shows the topology and routing for the DQS and D net class; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

Figure 5-22. DQS and D Routing and Topology

Table 5-35. DQS and D Routing Specification

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center to center DQS to other DDR2/mDDR trace spacing(1)

4w(2)

DQS/D nominal trace length(3)(4)

DQLM-50

DQLM

DQLM+50

Mils

D to DQS Skew Length Mismatch(4)

100

Mils

D to D Skew Length Mismatch(4)

100

Mils

Center to center D to other DDR2/mDDR trace spacing(1)(5)

4w(2)

Center to Center D to other D trace spacing(1)(6)

3w(2)

(1)

Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2)

w = PCB trace width as defined in Table 5-27.

(3)

Series terminator, if used, should be located closest to DDR.

(4)

There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte

(5)

D's from other DQS domains are considered other DDR2/mDDR trace.

(6)

DQLM is the longest Manhattan distance of each of the DQS and D net class.

Peripheral Information and Electrical Specifications

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