AFE5808A datasheet(61/66 Pages) TI1

61 / 66 page

500 Ω

I/VSum

Amp

Cext

Rint/Rext

CW_OUTM

CW_OUTP

LNA

INP

INM

ACT

INPUT

CW_AMPINM

CW_AMPINP

Mixer

Clock

PGA_P

PGA_M

Cext

5 K

500 Ω

S0504-01

AFE5808A

www.ti.com

SLOS729B – OCTOBER 2011 – REVISED APRIL 2012

Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down

Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0]. Based on the buffer amplifier configuration, the registers

can be set in different ways:

Configuration 1:

In this configuration, the test outputs can be monitored at CW_AMPINP/M

•

Reg59[9]=1 ;Test mode enabled

•

Reg59[8]=0 ;Buffer amplifier powered down

Configuration 2:

In this configuration, the test outputs can be monitored at CW_OUTP/M

•

Reg59[9]=1 ;Test mode enabled

•

Reg59[8]=1 ;Buffer amplifier powered on

•

Reg54[4:0]=10H; Internal feedback 2K resistor enabled. Different values can be used as well

Figure 92. AFE5808A PGA Test Mode

POWER SUPPLY, GROUNDING AND BYPASSING

In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5808A

distinguishes between two different grounds: AVSS(Analog Ground) and DVSS(digital ground). In most cases, it

should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the AFE5808A.

Care should be taken that this ground plane is properly partitioned between various sections within the system to

minimize interactions between analog and digital circuitry. Alternatively, the digital (DVDD) supply set consisting

of the DVDD and DVSS pins can be placed on separate power and ground planes. For this configuration, the

AVSS and DVSS grounds should be tied together at the power connector in a star layout. In addition, optical

isolator or digital isolators, such as ISO7240, can separate the analog portion from the digital portion completely.

Consequently they prevent digital noise to contaminate the analog portion. Table 13 lists the related circuit blocks

for each power supply.

Table 14. Supply vs Circuit Blocks

POWER SUPPLY

GROUND

CIRCUIT BLOCKS

LNA, attenuator, PGA with current clamp

AVDD (3.3VA)

AVSS

and BPF, reference circuits, CW summing

amplifier, CW mixer, VCA SPI

AVDD_5V (5VA)

AVSS

LNA, CW clock circuits, reference circuits

AVDD_ADC (1.8VA)

AVSS

ADC analog and reference circuits

DVDD (1.8VD)

DVSS

LVDS and ADC SPI

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