HC165 datasheet(5/7 Pages) SLS

5 / 7 page

SL74HC165

System Logic

Semiconductor

SLS

TIMING REQUIREMENTS (C

L=50pF,Input t r=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

°C to

-55

°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, Parallel

Data Inputs to Serial

Shift/Parallel Load (Figure 4)

2.0

4.5

6.0

100

125

150

tSU

Minimum Setup Time, Input SA

to Clock (or Clock Inhibit)

(Figure 5)

2.0

4.5

6.0

100

125

150

tSU

Minimum Setup Time, Serial

Shift/Parallel Load to Clock (or

Clock Inhibit) (Figure 6)

2.0

4.5

6.0

100

125

150

tSU

Minimum Setup Time, Clock to

Clock Inhibit (Figure 7)

2.0

4.5

6.0

100

125

150

Minimum Hold Time, Serial

Shift/Parallel Load to Parallel

Data Inputs (Figure 4)

2.0

4.5

6.0

Minimum Hold Time, Clock (or

Clock Inhibit) to Input SA

(Figure 5)

2.0

4.5

6.0

Minimum Hold Time, Clock (or

Clock Inhibit) to Serial

Shift/Parallel Load (Figure 6)

2.0

4.5

6.0

trec

Minimu m Recovery Time,

Clock to Clock Inhibit

(Figure 7)

2.0

4.5

6.0

100

125

150

Minimum Pulse Width, Clock

(or Clock Inhibit) (Figure 1)

2.0

4.5

6.0

100

120

Minimum Pulse Width, Serial

Shift/Parallel Load (Figure 2)

2.0

4.5

6.0

100

120

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

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