DAC712PLG4 datasheet(17/23 Pages) TI1

17 / 23 page

10kW

±10VVOUT

DAC712

9.75kW

IDAC

0mA-2mA

15kW

20kW

0Vto+10V

10kW

170W

250W

Internal

+10VReference

REFOUT

GainAdjust

(1)

BipolarOffsetAdjust

(1)

340W

500W

FB VREFA

FB VREFB

0Vto10V

5kW

10kW

+10V

10kW

-10V

(2)

(3)

(4)

DIGITAL INTERFACE

BUS INTERFACE

SINGLE-BUFFERED OPERATION

enabled by connecting

to DCOM. If A1 is not used

is the enable control for the DATA INPUT LATCH.

is the enable for the D/A LATCH. WR is used to

strobe data into latches enabled by

and A1. Refer

TRANSPARENT INTERFACE

transparent by asserting

, A1, and WR LOW, and

DAC712

www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009

(1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R1 to R4 tolerance is ±1% values. Range of adjustment

is at least ±0.3% FSR.

(2) Suggested op amps: OPA177GP, GS or OPA604AP, AU.

(3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU.

(4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dual

DAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bit

resolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for 0V to +10V output; no op-amps required).

Figure 14. Gain and Offset Adjustment Using D/A Converters

The DAC712 has 16-bit, double-buffered data bus

To operate the DAC712 interface as a single-buffered

interface with control lines for easy interface to

latch, the DATA INPUT LATCH is permanently

interface to a 16-bit bus. The double-buffered feature

permits

update

several

D/A

converters

to enable the D/A converter, it should be connected

simultaneously.

to DCOM as well. For this mode of operation, the

width of WR must be at least 80ns minimum to pass

data through the DATA INPUT LATCH and into the

D/A LATCH.

to the block diagram of Figure 8 and to Figure 1.

CLR sets the INPUT DATA LATCH to all zeros and

The digital interface of the DAC712 can be made

the D/A LATCH to a code that gives bipolar 0V at the

D/A converter output.

asserting CLR HIGH.

Submit Documentation Feedback

Product Folder Link(s): DAC712

DAC712PLG4 bảng dữ liệu(PDF) 17 Page - Texas Instruments

DAC712PLG4 bảng dữ liệu(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

bảng dữ liệu tải về

Link URL