HC109 datasheet(4/5 Pages) SLS

4 / 5 page

SL74HC109

System Logic

Semiconductor

SLS

AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

25 °C to

-55°C

≤85°C

≤125°C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

4.8

4.0

MHz

tPLH, tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

4.5

6.0

175

220

265

tPLH, tPHL

Maximum Propagation Delay , Set or Reset to Q or

Q (Figures 2 and 4)

2.0

4.5

6.0

230

290

345

tTLH, tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

110

CIN

Maximum Input Capacitance

Power Dissipation Capacitance (Per Flip-Flop)

Typical @25°C,VCC=5.0 V

CPD

Used to determine the no-load dynamic power

consumption: PD=CPDVCC

f+ICCVCC

TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)

VCC

Guaranteed Limit

Symbol

Parameter

25 °C to -55°C

≤85°C

≤125°C

Unit

tSU

Minimum Setup Time, J or K to

Clock (Figure 3)

2.0

4.5

6.0

100

125

150

Minimum Hold Time, Clock to

J or K (Figure 3)

2.0

4.5

6.0

trec

Minimum Recovery Time, Set

or Reset Inactive to Clock

(Figure 2)

2.0

4.5

6.0

Minimum Pulse Width, Set or

Reset (Figure 2)

2.0

4.5

6.0

100

Minimum Pulse Width,Clock

(Figure 1)

2.0

4.5

6.0

100

tr, tf

Maximum Input Rise and Fall

Times (Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

HC109 bảng dữ liệu(PDF) 4 Page - System Logic Semiconductor

HC109 bảng dữ liệu(HTML) 4 Page - System Logic Semiconductor

Html Pages

1 2 3 4 5

bảng dữ liệu tải về

Link URL