Programmer datasheet(10/15 Pages) CYPRESS

10 / 15 page

CY25200

Document Number: 38-07633 Rev. *H

Page 10 of 15

AC Electrical Specifications

Parameter

Description

Condition

Min

Typ

Max

Unit

Output Duty Cycle

SSCLK, Measured at VDD/2

Output Duty Cycle

REFCLK, Measured at VDD/2

Duty Cycle of CLKIN = 50%.

SR1

Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3 V

0.6

–

2.0

V/ns

SR2

Rising/Falling Edge Slew Rate SSCLK1/2/3/4

100 MHz, VDD = VDDL = 3.3 V

0.8

–

3.5

V/ns

SR3

Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5 V

0.5

–

2.2

V/ns

SR4

Rising/Falling Edge Slew Rate SSCLK1/2/3/4

100 MHz, VDD = VDDL = 2.5 V

0.6

–

3.0

V/ns

SR5

Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3 V

0.6

–

1.9

V/ns

SR6

Rising/Falling Edge Slew Rate SSCLK5/6

100 MHz, VDD = VDDL = 3.3 V

1.0

–

2.9

V/ns

TCCJ1

Cycle-to-Cycle Jitter

SSCLK1/2/3/4

CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and

SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

––

110

CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

170

CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

140

CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

290

TCCJ2

Cycle-to-Cycle Jitter

SSCLK5/6=REFOUT

CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and

SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

100

CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

120

CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

180

CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V

–

180

TCCJ3

Cycle-to-Cycle Jitter

SSCLK1/2/3/4

CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and

SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V

––

110

CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V

–

170

CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V

–

190

CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread

and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V

–

330

TSTP

Power Down Time

Time from falling edge on PD# to stopped outputs

(Asynchronous)

–

150

300

TOE1

Output Disable Time

Time from falling edge on OE to stopped outputs

(Asynchronous)

–

150

300

TOE2

Output Enable Time

Time from rising edge on OE to outputs at a valid

frequency (Asynchronous)

–

150

300

FMOD

Spread Spectrum Modulation

Frequency

SSCLK1/2/3/4/5/6

30.0

31.5

33.0

kHz

TPU1

Power Up Time,

Crystal is used

Time from rising edge on PD# to outputs at valid

frequency (Asynchronous)

–3

TPU2

Power Up Time,

Reference clock is used

Time from rising edge on PD# to outputs at valid

frequency (Asynchronous)

–2

TSKEW[4]

Clock Skew

Output to output skew between related clock outputs.

Measured at VDD/2.

–

250

Note

4. Skew and phase alignment is guaranteed within all SSCLK outputs and within both REFOUT outputs. All SSCLK outputs are related, and all REOUT outputs are

related, but SSCLK and REFOUT outputs are not related to each other.

[+] Feedback

Programmer bảng dữ liệu(PDF) 10 Page - Cypress Semiconductor

Programmer bảng dữ liệu(HTML) 10 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

bảng dữ liệu tải về

Link URL