CY7C09279V-7AXC datasheet(1/22 Pages) CYPRESS

tên linh kiện	CY7C09279V-7AXC

Giải thích chi tiết về linh kiện	3.3 V 16 K / 32 K / 64 K 횞 16 / 18 Synchronous Dual-Port Static RAM

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nhà sản xuất	CYPRESS [Cypress Semiconductor]

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CY7C09269V/79V/89V

CY7C09369V/89V

3.3 V 16 K / 32 K / 64 K × 16 / 18

Synchronous Dual-Port Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

, CA 95134-1709

•

408-943-2600

Document Number: 38-06056 Rev. *I

Revised August 1, 2012

3.3 V 16 K / 32 K / 64 K × 16 / 18 Synchronous Dual-Port Static RAM

Features

■ True dual-ported memory cells that allow simultaneous access

of the same memory location

■ Six flow through/pipelined devices:

❐ 16 K × 16 / 18 organization (CY7C09269V/369V)

❐ 32 K × 16 organization (CY7C09279V)

❐ 64 K × 16 / 18 organization (CY7C09289V/389V)

■ Three modes:

❐ Flow through

❐ Pipelined

❐ Burst

■ Pipelined output mode on both ports allows fast 100 MHz

operation

■ 0.35 micron CMOS for optimum speed and power

■ High speed clock to data access: 7.5

[1], 9, 12 ns (max)

■ 3.3 V low operating power:

❐ Active = 115 mA (typical)

❐ Standby = 10 A (typical)

■ Fully synchronous interface for easier operation

■ Burst counters increment addresses internally:

❐ Shorten cycle times

❐ Minimize bus noise

❐ Supported in flow through and pipelined modes

■ Dual chip enables easy depth expansion

■ Upper and lower byte controls for bus matching

■ Automatic power down

■ Commercial and industrial temperature ranges

■ Pb-free 100-pin TQFP package available

R/

WL

1

0

0/1

CE0L

CE1L

LBL

OEL

UBL

1b

0/1

0b 1a 0a

ba

FT

/PipeL

I/O8/9L–I/O15/17L

I/O0L–I/O7/8L

I/O

Control

Counter/

Address

Register

Decode

A0L–A13/14/15L

CLKL

ADSL

CNTENL

CNTRSTL

True Dual-Ported

RAM Array

R/

WR

1

0

0/1

CE0R

CE1R

LBR

OER

UBR

1b

0/1

0b

1a

0a

b

a

FT

/PipeR

I/O

Control

Counter/

Address

Register

Decode

14/15/16

8/9

I/O8/9R–I/O15/17R

I/O0R–I/O7/8R

A0R–A13/14/15R

CLKR

ADSR

CNTENR

CNTRSTR

14/15/16

8/9

[2]

[3]

[2]

[3]

[4]

Logic Block Diagram

Notes

1. See Figure 4 on page 8 for Load Conditions.

2. I/O8–I/O15 for × 16 devices; I/O9–I/O17 for × 18 devices.

3. I/O0–I/O7 for × 16 devices. I/O0–I/O8 for × 18 devices.

4. A0–A13 for 16K; A0–A14 for 32K; A0–A15 for 64K devices.

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nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Cypress Semiconductor	CY7C09279V-7AXC	758Kb / 19P	3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM

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