SL4029BN datasheet(5/8 Pages) SLS

tên linh kiện	SL4029BN

Giải thích chi tiết về linh kiện	Presettable Up/Down Counter

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nhà sản xuất	SLS [System Logic Semiconductor]

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SL4029B

System Logic

Semiconductor

SLS

TIMING REQUIREMENTS(C

L=50pF, RL=200 k

Ω, Input t

r=tf=20 ns)

VCC

Guaranteed Limit

Symbol

Parameter

≥-55°C

°C

≤125°C

Unit

Minimum Pulse Width, Clock (Figure 1)

5.0

180

360

180

120

Minimum Pulse Width, Preset Enable

(Figure 1)

5.0

130

260

140

100

tsu

Minimum Setup Time, Clock to B/D or U/D

(Figure 1)

5.0

340

140

100

340

140

100

680

280

200

trem

Minimum Removal Time, Preset Enable (Figure 1)

5.0

200

110

200

110

400

220

160

Minimum Hold Time, Clock to Carry In (Figure 2)

5.0

100

tsu

MinimumSetup Time, Carry In to Clock (Figure

5.0

200

400

140

120

tr, tf

Maximum Input Rise and Fall Times,Clock

(Figure 2)

5.0

µs

* From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.

** From Carry In to Clock Edge

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