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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SP682 bảng dữ liệu(PDF) 3 Page - Sipex Corporation |
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SP682 bảng dữ liệu(HTML) 3 Page - Sipex Corporation |
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3 / 8 page  3 Date: 5/20/04 SP682 Micro Power Inverting Charge Pump © Copyright 2004 Sipex Corporation about 12kHz (20kHz maximum) which con- serves power as opposed to higher frequency which operation typically draws more power from V CC. The external charge pump capacitors specified are 3.3 µF but the absolute minimum should be 1 µF. EFFICIENCY INFORMATION A charge pump theoretically produces a doubled voltage at 100% efficiency. However in the real world, there is a small voltage drop on the output which reduces the output efficiency. The SP682 can usually run 99.9% efficient without driving a load. While driving a 1k Ω load, the SP682 remains over 90% efficiency. Output Voltage Efficiency = V OUT / (–2*VCC); V OUT = –2*VCC + VDROP V DROP = (IOUT)*(ROUT) Power Loss = I OUT*(VDROP) The efficiency changes as the external charge pump capacitors are varied. Larger capacitor values will strengthen the output and reduce output ripple. Although smaller capacitors will cost less and save board space, lower values will reduce the output drive capability and also in- crease the output ripple. Figure 3. Charge Pump Phase 2 Figure 2. Charge Pump Phase 1 The SP682's charge pump design is a simpli- fied version of Sipex's original patented charge pump design (5,306,954) except that it only generates a negative output. The charge pump utilizes external capacitors to store the charge. Figure 1 shows the waveform found on the negative side of capacitor C2. There is a free– running oscillator, running at 12kHz, that con- trols the two phases of the voltage shifting. A description of each phase follows. Phase 1 V OUT charge storage — During this phase of the clock cycle, the positive side of capacitors C 1 and C2 are initially charged to +5V. Cl + is then switched to ground and the charge on C 1 – is transferred to C 2 –. Since C 2 + is connected to +5V, the voltage potential across capacitor C 2 is now 10V. Phase 2 V OUT transfer — Phase two of the clock con- nects the negative terminal of C 2 to the VOUT storage capacitor and the positive terminal of C 2 to ground, and transfers the generated –l0V to C 3. Simultaneously, the positive side of capacitor C 1 is switched to +5V and the nega- tive side is connected to ground. The oscillator frequency or clock rate for the charge pump is designed for low power opera- tion. The oscillator operates at a frequency of Figure 1. Charge Pump Waveform VCC = +5V –5V –5V +5V C1 C2 ++ – – VOUT Storage Capacitor C3 + – VCC = +5V –10V C1 C2 ++ – – VOUT Storage Capacitor C3 + – THEORY OF OPERATION |
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