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MMA7660FCT bảng dữ liệu(PDF) 16 Page - Freescale Semiconductor, Inc

tên linh kiện MMA7660FCT
Giải thích chi tiết về linh kiện  3-Axis Orientation/Motion Detection Sensor
PDF  35 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA7660FCT bảng dữ liệu(HTML) 16 Page - Freescale Semiconductor, Inc

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Sensors
Freescale Semiconductor, Inc.
16
MMA7660FC
$06: Interrupt Setup Register
INTSU
FBINT
0: Front/Back position change does not cause an interrupt
1: Front/Back position change causes an interrupt
PLINT
0: Up/Down/Right/Left position change does not cause an
interrupt
1: Up/Down/Right/Left position change causes an interrupt
PDINT
0: Successful tap detection does not cause an interrupt
1: Successful tap detection causes an interrupt
ASINT
0: Exiting Auto-Sleep does not cause an interrupt
1: Exiting Auto-Sleep causes an interrupt
GINT
0: There is not an automatic interrupt after every
measurement
1: There is an automatic interrupt after every measurement,
when g-cell readings are updated in XOUT, YOUT, ZOUT
registers, regardless of whether the readings have changed
or not. This interrupt does not affect the Auto-Sleep or Auto-
Wake functions.
SHINTX
0: Shake on the X-axis does not cause an interrupt or set the
Shake bit in the TILT register
1: Shake detected on the X-axis causes an interrupt, and sets
the Shake bit in the TILT register
SHINTY
0: Shake on the Y-axis does not cause an interrupt or set the
Shake bit in the TILT register
1: Shake detected on the Y-axis causes an interrupt, and sets
the Shake bit in the TILT register
SHINTZ
0: Shake on the Z-axis does not cause an interrupt or set the
Shake bit in the TILT register
1: Shake detected on the Z-axis causes an interrupt, and sets
the Shake bit in the TILT register.
The active interrupt condition (IRQ = 0 if IAH = 0, IRQ = 1 if IAH = 1) is released during the acknowledge bit of the slave address
transmission of the first subsequent I2C to MMA7660FC after the interrupt was asserted.
D7
D6
D5
D4
D3
D2
D1
D0
SHINTX
SHINTY
SHINTZ
GINT
ASINT
PDINT
PLINT
FBINT
00
00
00
00



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