LTM9012 datasheet(15/28 Pages) LINER

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LTM9012

9012f

applicaTions inForMaTion

Figure 5. Sinusoidal Encode Drive

Figure 6. PECL or LVDS Encode Drive

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should be

treatedasanalogsignals—donotroutethemnexttodigital

traces on the circuit board. There are two modes of opera-

tion for the encode inputs: the differential encode mode

(Figure 3), and the single-ended encode mode (Figure 4).

Thedifferentialencodemodeisrecommendedforsinusoi-

dal, PECL, or LVDS encode inputs (Figure 5 and Figure 6).

The encode inputs are internally biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

Figure 3. Equivalent Encode Input Circuit

for Differential Encode Mode

Figure 4. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

VDD

LTM9012

9012 F03

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

ENC+

ENC–

9012 F04

1.8V TO 3.3V

LTM9012

CMOS LOGIC

BUFFER

50Ω

100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTM9012

9012 F05

ENC–

ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1µF

9012 F06

LTM9012

above VDD (up to 3.6V), and the common mode range is

from 1.1V to 1.6V. In the differential encode mode, ENC–

should stay at least 200mV above ground to avoid falsely

triggering the single-ended encode mode. For good jitter

performance ENC+ should have fast rise and fall times.

Thesingle-endedencodemodeshouldbeusedwithCMOS

encode inputs. To select this mode, ENC– is connected

to ground and ENC+ is driven with a square wave encode

input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V

to3.3VCMOSlogiclevelscanbeused.TheENC+threshold

is 0.9V. For good jitter performance ENC+ should have fast

rise and fall times.

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