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LTC4258 bảng dữ liệu(PDF) 5 Page - Linear Technology

tên linh kiện LTC4258
Giải thích chi tiết về linh kiện  Synchronous No-Opto Flyback Controller
PDF  42 Pages
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nhà sản xuất  LINER [Linear Technology]
Trang chủ  http://www.linear.com
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LTC4258 bảng dữ liệu(HTML) 5 Page - Linear Technology

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LTC4278
5
4278fc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
respect to VNEG.
Note 4: All voltages are with respect to VPORTN pin unless otherwise noted.
Note 5: Input voltage specifications are defined with respect to LTC4278
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
Note 6: Signature resistance is measured via the ∆V/∆I method with the
minimum ∆V of 1V. The LTC4278 signature resistance accounts for the
additional series resistance in the input diode bridge.
Note 7: An invalid signature after the 1st classification event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/RCLASS and does not include variations in RCLASS resistance.
Note 9: This parameter is assured by design and wafer level testing.
Note 10: VCC = 14V; PG, SG Open; VCMP = 1.4V, VSENSE– = 0V, RCMP = 1k,
RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified. All
voltages are with respect to GND.
Note 11: Supply current does not include gate charge current to the
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Compensation
Load Compensation to VSENSE Offset
Voltage
VRCMP with VSENSE+ = 0V
0.8
mV
Feedback Pin Load Compensation Current
VSENSE+ = 20mV, VFB = 1.230V
20
µA
UVLO Function
UVLO Pin Threshold (VUVLO)
l
1.215
1.240
1.265
V
UVLO Pin Bias Current
VUVLO = 1.2V
VUVLO = 1.3V
–0.25
–4.50
0.1
–3.4
0.25
–2.50
µA
µA



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