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ADS4128 bảng dữ liệu(PDF) 49 Page - Texas Instruments

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tên linh kiện ADS4128
Giải thích chi tiết về linh kiện  12-Bit, 200-MSPS, Ultralow-Power ADC
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ADS4128 bảng dữ liệu(HTML) 49 Page - Texas Instruments

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V
DIFF
V
DIFF
1.1 V
High
Low
Low
High
OUTP
OUTM
R
OUT
External
100-
Load
W
ADS4128
www.ti.com
SBAS578 – MAY 2012
LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 52. After reset, the buffer presents a 100-
Ω
output impedance to match the external 100-
Ω termination.
VDIFF voltage is nominally 350 mV, resulting in a ±350-mV output swing with a 100-Ω external termination. VDIFF
voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the LVDS buffer strength to support 50-
Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100-
Ω
termination. This mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
NOTE: Use the default buffer strength to match the 100-
Ω external termination (ROUT = 100 Ω). To match with a 50-Ω external termination,
set the LVDS STRENGTH bit (ROUT = 50 Ω).
Figure 52. LVDS Buffer Equivalent Circuit
Copyright © 2012, Texas Instruments Incorporated
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