SSM2518CBZ-R7 datasheet(35/48 Pages) AD

35 / 48 page

Data Sheet

SSM2518

Rev. A | Page 35 of 48

POWER AND FAULT CONTROL REGISTER

Address: 0x09, Reset: 0x99, Name: Power_Fault_Control

Table 22. Bit Descriptions for Power_Fault_Control

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

AR_TIME

Automatic Recovery Delay Time. This determines the amount of time

delay between fault detection and an autorecovery attempt.

0x2

10 ms autorecovery delay

20 ms autorecovery delay

40 ms autorecovery delay

80 ms autorecovery delay

RESERVED

Reserved.

0x0

AMP_LPM

Class-D Amplifier Low Power Mode.

0x1

High performance operation

Low power operation

DAC_LPM

DAC Low Power Mode. In low power mode, the DAC runs at half speed.

0x1

Normal operation

Low power operation

R_PWDN

Right Channel Power-Down.

0x0

Normal operation

Right channel powered down

L_PWDN

Left Channel Power-Down.

0x0

Normal operation

Left channel powered down

APWDN_EN

Automatic Power-Down Enable. Automatic power-down automatically

puts the IC in a low power state when 2048 consecutive zero input

samples have been received.

0x1

Automatic power-down disabled

Automatic power-down enabled

SSM2518CBZ-R7 bảng dữ liệu(PDF) 35 Page - Analog Devices

SSM2518CBZ-R7 bảng dữ liệu(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

bảng dữ liệu tải về

Link URL