AD6672 datasheet(25/32 Pages) AD

25 / 32 page

AD6672

Rev. 0 | Page 25 of 32

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into four sections: the chip

configuration registers (Address 0x00 to Address 0x02); the transfer

setup, control, and test (Address 0x08 to Address 0x25); and the

digital feature control registers (Address 0x3C and Address 0x3E).

The memory map register table (Table 13) documents the

default hexadecimal value for each hexadecimal address shown.

The Bit 7 (MSB) column is the start of the default hexadecimal

value given. For example, Address 0x14, the output mode

that Bit 0 = 1 and the remaining bits are 0s. This setting is the

default output format value, which is twos complement. For

more information on this function and others, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI. This

document details the functions controlled by Register 0x00 to

Description section.

Open Locations

All address and bit locations that are not included in Table 13

are not currently supported for this device. Write 0s to unused

bits of a valid address location. Writing to these locations is

required only when part of an address location is open (for

example, Address 0x18). If the entire address location is open

(for example, Address 0x13), this address location should not be

written.

Default Values

After the AD6672 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (Table 13).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x20, as well as Address 0x3C and

Address 0x3E, are shadowed. Writes to these addresses do not

affect part operation until a transfer command is issued by

writing 0x01 to Address 0xFF, setting the transfer bit. This allows

these registers to be updated internally and simultaneously when

the transfer bit is set. The internal update takes place when the

transfer bit is set, and then the bit autoclears.

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