AD5791 datasheet(19/28 Pages) AD

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Data Sheet

AD5780

Rev. C | Page 19 of 28

THEORY OF OPERATION

The AD5780 is a high accuracy, fast settling, single, 18-bit,

serial input, voltage output DAC. It operates from a VDD supply

voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V.

Data is written to the AD5780 in a 24-bit word format via a 3-wire

serial interface. The AD5780 incorporates a power-on reset

circuit that ensures the DAC output powers up to 0 V with the

VOUT pin clamped to AGND through a ~6 kΩ internal resistor.

DAC ARCHITECTURE

The architecture of the AD5780 consists of two matched DAC

sections. A simplified circuit diagram is shown in Figure 50.

The six MSBs of the 18-bit data-word are decoded to drive

63 switches, E0 to E62. Each of these switches connects one

of 63 matched resistors to either the buffered VREFP or buffered

VREFN voltage. The remaining 12 bits of the data-word drive

the S0 to S11 switches of a 12-bit voltage mode R-2R ladder

network.

S11

E62

E61

12-BIT R-2R LADDER

...

VOUT

SIX MSBs DECODED INTO

63 EQUAL SEGMENTS

VREFP

VREFN

Figure 50. DAC Ladder Structure Serial Interface

SERIAL INTERFACE

The AD5780 has a 3-wire serial interface (SYNC, SCLK, and

SDIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards, as well as most DSPs (see

for a

timing diagram).

Figure 2

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK, which can operate at up to 35 MHz. The

input register consists of a R/W bit, three address bits, and

20 data bits as shown in

. The timing diagram for this

operation is shown in

Table 6

Figure 2

Table 6. Input Shift Register Format

MSB

LSB

DB23

DB22

DB21

DB20

DB19 to DB0

R/W

Table 7. Decoding the Input Shift Register

R/W

Description

No operation (NOP). Used in readback operations.

Write to the DAC register.

Write to the control register.

Write to the clearcode register.

Write to the software control register.

Read from the DAC register.

Read from the control register.

Read from the clearcode register.

1 X is don’t care.

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