U7313

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

9 of 14

www.unisonic.com.tw

QW-R502-173.B

ACKNOWLEDGE

The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The slave which

acknowledge pull down the SDA line during the acknowledge clock pulse. The SDA line keep in a stable low state.

The slave which has been addressed has to generate an acknowledge after receiving each byte. If the SDA line still

at the high level during the ninth clock pulse time, the master can generate the stop information to abort the transfer.

If want to abort the acknowledge information, the master can stop detecting the acknowledge by waits one clock

without checking, then sends the new data. This approach of course is less protected from misoperation and

decrease the noise immunity.