AGL015 datasheet(51/248 Pages) MICROSEMI

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IGLOO Low Power Flash FPGAs

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Detailed I/O DC Characteristics

Table 2-37 • Input Capacitance

Symbol

Definition

Conditions

Min.

Max.

Units

CIN

Input capacitance

VIN = 0, f = 1.0 MHz

CINCLK

Input capacitance on the clock pin

VIN = 0, f = 1.0 MHz

Table 2-38 • I/O Output Buffer Maximum Resistances1

Applicable to Advanced I/O Banks

Standard

Drive Strength

RPULL-DOWN

(

Ω)2

RPULL-UP

(

Ω)3

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

100

300

4 mA

100

300

6 mA

150

8 mA

150

12 mA

16 mA

24 mA

3.3 V LVCMOS Wide Range

100

μATBD

TBD

2.5 V LVCMOS

2 mA

100

200

4 mA

100

200

6 mA

100

8 mA

100

12 mA

16 mA

1.5 V LVCMOS

2 mA

200

224

4 mA

100

112

6 mA

8 mA

12 mA

1.2 V LVCMOS4

2 mA

TBD

1.2 V LVCMOS Wide Range4

100

μATBD

TBD

3.3 V PCI/PCI-X

Per PCI/PCI-X

specification

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

4. Applicable to IGLOO V2 Devices operating at VCCI

≥ VCC

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