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PP0640SC bảng dữ liệu(PDF) 6 Page - Protek Devices

tên linh kiện PP0640SC
Giải thích chi tiết về linh kiện  THYRISTOR SURGE SUPPRESSOR
PDF  9 Pages
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nhà sản xuất  PROTEC [Protek Devices]
Trang chủ  http://www.protekdevices.com
Logo PROTEC - Protek Devices

PP0640SC bảng dữ liệu(HTML) 6 Page - Protek Devices

  PP0640SC Datasheet HTML 1Page - Protek Devices PP0640SC Datasheet HTML 2Page - Protek Devices PP0640SC Datasheet HTML 3Page - Protek Devices PP0640SC Datasheet HTML 4Page - Protek Devices PP0640SC Datasheet HTML 5Page - Protek Devices PP0640SC Datasheet HTML 6Page - Protek Devices PP0640SC Datasheet HTML 7Page - Protek Devices PP0640SC Datasheet HTML 8Page - Protek Devices PP0640SC Datasheet HTML 9Page - Protek Devices  
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Only One Name Means ProTek’Tion™
www.protekdevices.com
05081.R11 2/11
Page 6
PP0640SA - PP3500SC
APPliCATion inFoRmATion
FiguRe 3 - ul 1459 & FCC PART 68 meTAlliC & longiTuDinAl PRoTeCTion
Three equal TSS devices are used in this application for metallic (tip-to-ring) and longitudinal (tip-to-ground and ring-to-ground) protection. For analog signals, the
PP3100SB/SC is recommended. With a resistance value of 15 Ohms for the tip and ring resistors, the PP3100SA may be used. The National Electric Code (NEC) article
800 requires two fuse elements when connecting to ground. Fuses or a suitable Positive Temperature Coefficient (PTC) automatic resettable current limiting device
may be used. This circuit is recommended for protection against the Bellcore requirement: First Level Lightning Surge Tests (Telecommunications Port), document #
GR-1089-CORE.
To Protected
Equipment
TIP
RING
R
Tip
R
Ring
CiRCuiT boARD ReCommenDATionS
Circuit board layout is critical for electromagnetic compatibility protection. The following guidelines are recommended:
• The protection device should be placed near the input terminals or connectors, the device will divert the transient current
immediately before it can be coupled into the nearby traces.
• The path length between the TVS device and the protected line should be minimized.
• All conductive loops including power and ground loops should be minimized.
• The transient current return path to ground should be kept as short as possible to reduce parasitic inductance.
• Ground planes should be used whenever possible. For multilayer PCBs, use ground vias.



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