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5

5 - 3

DISC

ONT

INUE

D

PRO

DUC

T

Not R

ecom

men

ded

for N

ew D

esig

ns

Worst Case Step Error

Between Successive Attenuation States

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

0

0.5

1

1.5

2

2.5

3

3.5

4

FREQUENCY (GHz)

Timing Diagram

Truth Table

Control Voltage Input

C16

C8

C4

C2

C1

C0.5

High

High

High

High

High

High

reference

I.L.

High

High

High

High

High

Low

0.5 dB

High

High

High

High

Low

High

1 dB

High

High

High

Low

High

High

2 dB

High

High

Low

High

High

High

4 dB

High

Low

High

High

High

High

8 dB

Low

High

High

High

High

High

16 dB

Low

Low

Low

Low

Low

Low

31.5 dB

Any combination of the above states will provide an attenuation

approximately equal to the sum of the bits selected.

Digital Control Voltages

state

Vcc = +5V

Low

0 to 1.3V

High

3.5 to 5V

Parameter

symbol

Vcc = +5V

units

Min.

Max.

serial Input setup time

ts

20

-

ns

Hold time from serial

Input to shift Clock

th

0

-

ns

setup time from shift

Clock to Latch enable

tlsup

40

-

ns

Latch enable Window,

Latch enable to C0.5

through C8

tpd

-

30

ns

setup time from reset to

shift Clock

-

20

-

ns

Clock Frequency

(1/tclk)

fclk

-

30

MHz

Timing

Serial Input Truth Table

Latch

enable

shift

Clock

reset

Function

X

X

L

shift register cleared

X

á

H

shift register clocked

á

X

H

Contents of shift register

transferred to Digital

Attenuator

HMC542LP4 / 542LP4E

v03.0809

0.5 dB LSB GaAs MMIC 6-BIT DIGITAL

SERIAL CONTROL ATTENUATOR, DC - 3 GHz