TS1002/TS1004

Touchstone Semiconductor, Inc.

Page 13

630 Alder Drive, Milpitas, CA 95035

TS1002_4DS r1p0

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RTFDS

PACKAGE OUTLINE DRAWING

14-Pin TSSOP Package Outline Drawing

(N.B., Drawings are not to scale)

Information furnished by Touchstone Semiconductor is believed to be accurate and reliable. However, Touchstone Semiconductor does not

assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use, and all

information provided by Touchstone Semiconductor and its suppliers is provided on an AS IS basis, WITHOUT WARRANTY OF ANY KIND.

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applications using Touchstone Semiconductor components. To minimize the risk associated with customer products and applications,

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respective owners.

DETAIL ‘A’

0.20 Max

0.09 Min

NOTE:

1. “D” AND “E” ARE REFERENCE DATUMS AND DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE.

2. “N” IS THE NUMBER OF TERMINAL POSITIONS.

3. CONTROLLING DIMENSION IN MILIMETERS AND ANGLES IN DEGREES.

4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153 AB-1

5. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC.

DETAIL ‘A’

0.30 Max

0.19 Min

SEATING PLANE

0.15 Max

O.05 Min

5.10 Max

4.90 Min

( D)

0.65 REF

1.05 Max

0.80 Min

1.20 Max

GAUGE PLANE

0.25

0' – 8'

1.00 REF

0.75 Max

0.45 Min

R = R’ = 0.09 Min

R’

0.25 Max

0.19 Min

0.30 Max

0.19 Min

0.20 Max

0.09 Min

0.16 Max

0.09 Min

12' TYP

ALL SIDES

0.10 Max

Pin 1

ID MARK

SEATING PLANE

1

2

N