ICS9E4101 datasheet(7/19 Pages) IDT

7 / 19 page

IDTTM

Programmable Timing Control HubTM for Intel Systems

1408A—01/25/10

ICS9E4101

Programmable Timing Control HubTM for Intel Systems

2C Table: Output Control Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

SRC Stop Drive Mode

Drive Mode in

PCI_Stop

Driven

Hi-Z

Bit 6

Bit 5

Bit 4

Bit 3

SRC PD Drive Mode

Drive Mode in PD

Driven

Hi-Z

Bit 2

CPUCLK_ITP

Drive Mode in PD

Driven

Hi-Z

Bit 1

CPUCLK1

Drive mode in PD

Driven

Hi-Z

Bit 0

CPUCLK0

Drive mode in PD

Driven

Hi-Z

2C Table: Output Control Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Test Mode Selection

Test Mode

Selection

Hi-Z

REF/N

Bit 6

Test Clock Mode Entry

Test Mode

Disable

Enable

Bit 5

Bit 4

REFOUT Strength

Strength Prog

Bit 3

PCI/SRC_STOP

Stop all PCI and

SRC clocks

Enabled, all

stoppable PCI

and SRC

clocks are

stopped.

Disabled, all

stoppable PCI

and SRC clocks

are running

Bit 2

FS_C

readback

LATCHED

Bit 1

FS_B

readback

LATCHED

Bit 0

FS_A

readback

LATCHED

2C Table: Vendor & Revision ID Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

2C Table: Byte Count Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

BC7

Bit 6

BC6

Bit 5

BC5

Bit 4

BC4

Bit 3

BC3

Bit 2

BC2

Bit 1

BC1

Bit 0

BC0

Byte 5

Byte 6

19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

RESERVED

17,18,19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

54,55,56,3,4,5,8,9,

19,20,22,23,

24,25,26,27,30,31,

32,33,35,36

35,36

REVISION ID

RESERVED

40,41

43,44

RESERVED

VENDOR ID

Byte 7

Byte 8

Writing to this

configure how

many bytes will be

read back, default

is 08 = 8 bytes.

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