UBA20271 datasheet(13/33 Pages) PHILIPS

13 / 33 page

UBA20271_UBA20272

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 12 October 2011

13 of 33

NXP Semiconductors

UBA20271/2

350 V and 600 V Power ICs for dimmable compact fluorescent lamps

7.3 Natural linear dimming

What determines the actual internal set point level used for the current control feedback

loop is an external level applied via the DCI pin for dimming. The DCI voltage is a function

of the phase cut angle of the applied dimmer. To ensure that the external input for the

control on the DCI pin internally stays within a certain range, this input signal passes an

internal linear to logarithmic conversion circuit followed by a limiting circuit.

The linear to logarithmic conversion circuit is designed to improve dimming control by

correcting for the higher sensitivity of the human eye to small changes in low light levels.

See Figure 10. The conversion circuit also provides a natural perceived linear brightness

adjustment of the lamp.

The limiting circuit prevents the signal falling below the MDL or rising above the 100 %

reference level of Vclamp(CSI). The output of the linear to logarithmic conversion circuit is

the actual reference voltage for the lamp current control loop. See signal VLD in Figure 1

(dimmer control block). When the IC is in the burn state, the voltage is equal to the RMS

voltage on the CSI pin. When the control loop is regulating correctly, the upper limit is

clamped at the 100 % reference level. This condition prevents lamp current values that

are too high in mains overvoltage situations. See Figure 10.

The MDL level presets a minimum to which the lamp current clips at low dim levels and is

adjustable via the MDL pin. An accurate minimum dimming voltage level is set by using an

internal reference current (derived from the internal band gap reference circuit and

resistor Rext(RREF)) and an applied external resistor RMDL on the MDL pin.

Fig 9.

Timing diagram preheat, ignition and overcurrent

001aam768

voltage

(V)

5 V

0 V

4.5 V

3.8 V

VCP

startup

time

preheat time

boost-burn

power down

overcurrent

fault time

CFL ignition

ignition

time

ignition

enabling time

time (s)

Vth(CP)max

Vth(CP)min

UBA20271 bảng dữ liệu(PDF) 13 Page - NXP Semiconductors

UBA20271 bảng dữ liệu(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

bảng dữ liệu tải về

Link URL