W25Q80BVZPAP datasheet(2/75 Pages) WINBOND

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W25Q80BV

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Table of Contents

GENERAL DESCRIPTION ............................................................................................................... 5

FEATURES....................................................................................................................................... 5

PIN CONFIGURATION SOIC 150 / 208-MIL ................................................................................... 6

PAD CONFIGURATION WSON 6X5-MM ........................................................................................ 6

PIN CONFIGURATION PDIP 300-MIL............................................................................................. 7

PIN DESCRIPTION SOIC 150/208-MIL, WSON 6X5-MM, AND PDIP 300-MIL.............................. 7

6.1

Package Types..................................................................................................................... 8

6.2

Chip Select (/CS).................................................................................................................. 8

6.3

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 8

6.4

Write Protect (/WP)............................................................................................................... 8

6.5

HOLD (/HOLD) ..................................................................................................................... 8

6.6

Serial Clock (CLK)................................................................................................................ 8

BLOCK DIAGRAM............................................................................................................................ 9

FUNCTIONAL DESCRIPTION ....................................................................................................... 10

8.1

SPI OPERATIONS ............................................................................................................. 10

8.1.1

Standard SPI Instructions.....................................................................................................10

8.1.2

Dual SPI Instructions ............................................................................................................10

8.1.3

Quad SPI Instructions...........................................................................................................10

8.1.4

Hold Function .......................................................................................................................10

8.2

WRITE PROTECTION ....................................................................................................... 11

8.2.1

Write Protect Features..........................................................................................................11

CONTROL AND STATUS REGISTERS ........................................................................................ 12

9.1

STATUS REGISTER .......................................................................................................... 12

9.1.1

BUSY....................................................................................................................................12

9.1.2

Write Enable Latch (WEL) ....................................................................................................12

9.1.3

Block Protect Bits (BP2, BP1, BP0)......................................................................................12

9.1.4

Top/Bottom Block Protect (TB).............................................................................................12

9.1.5

Sector/Block Protect (SEC) ..................................................................................................12

9.1.6

Complement Protect (CMP) .................................................................................................13

9.1.7

Status Register Protect (SRP1, SRP0).................................................................................13

9.1.8

Erase/Program Suspend Status (SUS) ................................................................................13

9.1.9

Security Register Lock Bits (LB3, LB2, LB1) ........................................................................13

9.1.10

Quad Enable (QE) ..............................................................................................................14

9.1.11

Status Register Memory Protection (CMP = 0)...................................................................15

9.1.12

Status Register Memory Protection (CMP = 1)...................................................................16

9.2

INSTRUCTIONS................................................................................................................. 17

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