ISL70001SEH

10

FN7956.0

November 30, 2011

To run the regulator from the internal oscillator, connect the M/S

pin to DVDD. In this case, the output of the internal oscillator

appears on the SYNC pin. To synchronize the regulator to the

SYNC output of another ISL70001SEH regulator or to an SEE

hardened external clock, connect the M/S pin to DGND. In this

case, the SYNC pin is an input that accepts an external

synchronizing signal. When synchronizing multiple devices, Slave

regulators are synchronized 180° out-of-phase with respect to

the SYNC output of a Master regulator or to an external clock.

Operation Initialization

The ISL70001SEH initializes based on the state of the power-on

reset (POR) monitor of the PVINx inputs and the state of the EN

input. Successful initialization prompts a soft-start interval, and

the regulator begins slowly ramping the output voltage. Once the

commanded output voltage is within the proper window of

operation, the power-good signal changes state from low to high,

indicating proper regulator operation.

Power-On Reset

The POR circuitry prevents the controller from attempting to

soft-start before sufficient bias is present at the PVINx pins.

The POR threshold of the PVINx pins is controlled by the PORSEL

pin. For a nominal 5V supply voltage, PORSEL should be

connected to DVDD. For a nominal 3.3V supply voltage, PORSEL

should be connected to DGND. For nominal supply voltages

between 5V and 3.3V, PORSEL should be connected to DGND.

The POR rising and falling thresholds are shown in the “Electrical

Specifications” table on page 8.

Hysteresis between the rising and falling thresholds ensures that

small perturbations on PVINx seen during turn-on/turn-off of the

regulator do not cause inadvertent turn-off/turn-on of the

regulator. When the PVINx pins are below the POR rising

threshold, the internal synchronous power MOSFET switches are

turned off, and the LXx pins are held in a high-impedance state.

Enable and Disable

After the POR input requirement is met, the ISL70001SEH

remains in shutdown until the voltage at the enable input rises

above the enable threshold. As shown in Figure 7, the enable

circuit features a comparator type input. In addition to simple

logic on/off control, the enable circuit allows the level of an

external voltage to precisely gate the turn-on/turn-off of the

11µA is only active when the voltage on the EN pin is below the

rises, the enable level is not set exclusively by the resistor divider

With the current sink active, the enable level is defined by

the resistor from the EN pin to the AGND pin.

Once the voltage at the EN pin reaches the enable threshold, the

level is set by the resistor divider. The disable level is defined by

Equation 5.

The difference between the enable and disable levels provides

with the enabling or disabling of the regulator.

To mitigate SEE, the EN pin should be bypassed to the AGND pin

with a 10nF ceramic capacitor.

Soft-Start

Once the POR and enable circuits are satisfied, the regulator

initiates a soft-start. Figure 8 shows that the soft-start circuit

clamps the error amplifier reference voltage to the voltage on an

external soft-start capacitor connected to the SS pin.

R1

R2

-------

+

⋅

⋅

+

=

(EQ. 4)

FIGURE 7. ENABLE CIRCUIT

-

+

EN

PVINx

POR

LOGIC

R1

R2

ENABLE

COMPARATOR

R1

R2

-------

+

⋅

=

(EQ. 5)

FIGURE 8. SOFT-START CIRCUIT

-

+

FB

PWM

LOGIC

ERROR

AMPLIFIER

REF

+

SS