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LPC11U2X bảng dữ liệu(PDF) 21 Page - NXP Semiconductors

tên linh kiện LPC11U2X
Giải thích chi tiết về linh kiện  32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USB device; USART
PDF  67 Pages
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nhà sản xuất  PHILIPS [NXP Semiconductors]
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LPC11U2X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 November 2011
21 of 67
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.15 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.16 Windowed WatchDog Timer (WWDT)
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.16.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
• Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
• Incorrect feed sequence causes reset or interrupt, if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.



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