71M6521FE datasheet(21/107 Pages) MAXIM

21 / 107 page

71M6521DE/DH/FE Data Sheet

Rev 2

Page: 21 of 107

Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the

operand. The mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.

B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad

Program Status Word (PSW):

MSB

LSB

RS1

Table 9: PSW Register Flags

Bit

Symbol

Function

PSW.7

Carry flag

PSW.6

Auxiliary Carry flag for BCD operations

PSW.5

General purpose Flag 0 available for user.

F0 is not to be confused with the F0 flag in the CE STATUS register.

PSW.4

RS1

RS1/RS0

Bank selected

Location

Bank 0

(0x00 – 0x07)

Bank 1

(0x08 – 0x0F)

Bank 2

(0x10 – 0x17)

Bank 3

(0x18 – 0x1F)

PSW.3

RS0

PSW.2

Overflow flag

PSW.1

User defined flag

PSW.0

Parity flag, affected by hardware to indicate odd / even number of “one” bits in the

Accumulator, i.e. even parity.

Table 10: PSW Bit Functions

Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented

before PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be

loaded as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g.

MOVC A,@A+DPTR or MOVX A,@DPTR respectively).

Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is

incremented when fetching operation code or when operating on data from program memory.

Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR

can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 11) causes the

corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level

(GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section

Digital I/O for details).

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