HT82V42 datasheet(18/24 Pages) HOLTEK

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HT82V42

Rev. 1.20

December 8, 2010

Bit

No.

Bit Name

POR

Description

Auto-cycle Reset

Writing to this register will cause the auto-cycle counter to be

reset to colour R. This function is only required when

LINEBYLINE=1. When this register is written, the reset func-

tion will be initiated immediately by an internal reset signal. If

the DCLK exists, the internal reset signal will keep active for

about 2 DCLK cycles. Otherwise, the device will keep in reset

state all the time.

Setup Register 4

LINEBYLINE

Select line by line mode

0: normal operation

1: line by line operation

ACYCNRLC

When LINEBYLINE=0, this bit has no effect

When LINEBYLINE=1, this bit controls the function of the

RLC/ACYC input signal and will control the multiplexer of the

offset/gain register.

0: RLC/ACYC pin enabled for Reset Level Clamp, internal se-

lection of input and offset/gain multiplexers.

1: Auto cycling enabled by pulsing the RLC/ACYC input pin.

RLCINT

This bit is used to determine whether the Reset Level

Clamping is used.

0: RLC disable

1: RLC enable

5~4

INTM[1:0]

Colour selection bits used for internal modes.

00: Red

01: Green

10: Blue

11: Reserved

Setup Register 5

VSMPDET

0: Normal operation, signal on the CDSCLK2 input pin is ap-

plied directly to the Timing Control Block

1: Programmable CDSCLK2 detect circuit is enabled. An in-

ternal synchronization pulse is generated from the signal

applied to the CDSCLK2 input pin and is applied to the Timing

Control Block.

3~1

VDEL[2:0]

000

When VSMPDEL=0, these bits have no effect.

When VSMPDEL=1, these bits set the programmable delay

from the detected edge of the signal on CDSCLK2. The inter-

nal generated pulse is delayed by VDEL DCLK periods from

the detected edge.

POSNNEG

When VSMPDEL=0, this bit has no effect

When VSMPDEL=1, this bit controls whether positive or neg-

ative edges are detected.

0: Negative edge on the CDSCLK2 pin is detected and used to

generate an internal timing pulse

1: Positive edge on the CDSCLK2 pin is detected and used to

generate an internal timing pulse

Setup Register 6

ClkMotr

Internal clock monitor.

0: normal active, OD[3:0] output ADC data.

1: internal clock test mode.

ClkMotr=0

ClkMotr=1

OD3

INTVSMP

OD2

Video sample clock

OD1

ADC clock

OD0

Reset sample clock

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