HT16C21 datasheet(18/34 Pages) HOLTEK

18 / 34 page

Rev. 1.00

November 22, 2011

HT16C21

Display RAM Read Operation

● In this mode, the master reads the HT16C21 data after setting the slave address. Following the R/W bit (=’0”)

is an acknowledge bit, a command byte and the register address byte which is written to the internal address

pointer. After the start address of the Read Operation has been configured, another START condition and the

slave address transferred on the I2C interface followed by the R/W bit (=’1”). Then the MSB of the data which

was addressed is transmitted first on the I2C interface. The address pointer is only incremented by 1 after the

reception of an acknowledge clock. That means that if the device is configured to transmit the data at the

address of AN+1, the master will read and acknowledge the transferred new data byte and the address pointer is

incremented to AN+2. After the internal address pointer reaches the maximum memory address, which is 09H

for 1/4 duty drive mode or 0FH for 1/8 duty drive mode, the address pointer will be reset to 00H.

● This cycle of reading consecutive addresses will continue until the master sends a STOP condition.

ACK

Write

ACK

Slave Address

S 0 1 1 1 0 0 0 0

Data byte

NACK

D7 D6 D5 D4 D3 D2 D1 D0

1st data

Data byte

ACK

D7 D6 D5 D4 D3 D2 D1 D0

Nth data

Data byte

D7 D6 D5 D4 D3 D2 D1 D0

2nd data

ACK

Device Address

Read

S 0 1 1 1 0 0 0 1

ACK

Command byte

1st

2nd

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

HT16C21 bảng dữ liệu(PDF) 18 Page - Holtek Semiconductor Inc

HT16C21 bảng dữ liệu(HTML) 18 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL