L3GD20TR datasheet(33/44 Pages) STMICROELECTRONICS

33 / 44 page

L3GD20

Doc ID 022116 Rev 1

33/44

7.4

CTRL_REG3 (22h)

Table 24.

High-pass filter mode configuration

HPM1

HPM0

High-pass filter mode

Normal mode (reset reading HP_RESET_FILTER)

Reference signal for filtering

Normal mode

Autoreset on interrupt event

Table 25.

High-pass filter cut off frequency configuration [Hz]

HPCF3-0

ODR=95 Hz

ODR=190 Hz

ODR=380 Hz

ODR=760 Hz

0000

7.2

13.5

51.4

0001

3.5

7.2

13.5

0010

1.8

3.5

7.2

13.5

0011

0.9

1.8

3.5

7.2

0100

0.45

0.9

1.8

3.5

0101

0.18

0.45

0.9

1.8

0110

0.090.180.450.9

0111

0.045

0.09

0.18

0.45

1000

0.018

0.045

0.09

0.18

1001

0.009

0.018

0.045

0.09

Table 26.

CTRL_REG1 register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 27.

CTRL_REG3 description

I1_Int1

Interrupt enable on INT1 pin. Default value 0. (0: disable; 1: enable)

I1_Boot

Boot status available on INT1. Default value 0. (0: disable; 1: enable)

H_Lactive

Interrupt active configuration on INT1. Default value 0. (0: high; 1:low)

PP_OD

Push-pull / Open drain. Default value: 0. (0: push- pull; 1: open drain)

I2_DRDY

Date-ready on DRDY/INT2. Default value 0. (0: disable; 1: enable)

I2_WTM

FIFO watermark interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

I2_ORun

FIFO overrun interrupt on DRDY/INT2 Default value: 0. (0: disable; 1: enable)

I2_Empty

FIFO empty interrupt on DRDY/INT2. Default value: 0. (0: disable; 1: enable)

L3GD20TR bảng dữ liệu(PDF) 33 Page - STMicroelectronics

L3GD20TR bảng dữ liệu(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

bảng dữ liệu tải về

Link URL