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TUSB8040RKMR bảng dữ liệu(PDF) 27 Page - Texas Instruments

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TUSB8040RKMR bảng dữ liệu(HTML) 27 Page - Texas Instruments

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TUSB8040
www.ti.com
SLLSE42F
– SEPTEMBER 2010 – REVISED OCTOBER 2011
6
ELECTRICAL SPECIFICATIONS
6.1
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VDD33
-0.3 to 3.8
Supply voltage
V
VDD11
-0.3 to 1.4
Tstg
Storage temperature range
-65 to 150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Expose to absolute-maximum-rated conditions for extended periods may affect device reliability
6.2
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD33
3
3.3
3.6
Supply voltage
V
VDD11
1.045
1.100
1.155
TA
Operating free-air temperature range
-40
25
85
°C
TJ
Operating junction temperature range
-40
25
105
°C
6.3
THERMAL INFORMATION
TUSB8040
THERMAL METRIC
PFP
UNITS
80 PINS
θJA
Junction-to-ambient thermal resistance(1)
24.8
θJCtop
Junction-to-case (top) thermal resistance(2)
21.5
θJB
Junction-to-board thermal resistance(3)
8.37
°C/W
ψJT
Junction-to-top characterization parameter(4)
0.5
ψJB
Junction-to-board characterization parameter(5)
8.2
θJCbot
Junction-to-case (bottom) thermal resistance(6)
1.6
(1)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright
© 2010–2011, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
27
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