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TUSB9261 bảng dữ liệu(PDF) 17 Page - Texas Instruments

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TUSB9261 bảng dữ liệu(HTML) 17 Page - Texas Instruments

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TUSB9261
www.ti.com
SLLSE67B
– MARCH 2011 – REVISED MAY 2011
6.3
Oscillator
XI should be tied to the 1.8-V clock source and XO should be left floating.
VSSOSC should be connected to the PCB ground plane.
A 20-, 25-, 30- or 40-MHz clock can be used.
Table 6-1. Oscillator Specification
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
CXI
XI input capacitance
TJ = 25°C
0.414
pF
VIL
Low-level input voltage
0.7
V
VIH
High-level input voltage
1.05
V
Ttosc_i
Frequency tolerance
Operational temperature
–50
50
ppm
Tduty
Duty cycle
45
50
55
%
TR/TF
Rise/Fall time
20% - 80 %
6
ns
RJ
Reference clock RJ
JTF (1 sigma)(1)(2)
0.8
ps
TJ
Reference clock TJ
JTF (total p-p)(2)(3)
25
ps
Tp-p
Reference clock jitter
(absolute p-p)(4)
50
ps
(1)
Sigma value assuming Gaussian distribution
(2)
After application of JTF
(3)
Calculated as 14.1 x RJ + DJ
(4)
Absolute phase jitter (p-p)
6.4
Crystal
A parallel, 20-pF load capacitor should be used if a crystal source is used.
VSSOSC should not be connected to the PCB ground plane.
A 20-, 25-, 30- or 40-MHz crystal can be used.
Table 6-2. Crystal Specification
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Oscillation mode
Fundamental
20
25
fO
Oscillation frequency
MHz
30
40
20 MHz and 25 MHz
50
ESR
Equivalent series resistance
30 MHz
40
Ω
40 MHz
30
Ttosc_i
Frequency tolerance
Operational temperature
±50
ppm
Frequency stability
1 year aging
±50
ppm
CL
Load capacitance
12
20
24
pF
Crystal and board stray
CSHUNT
4.5
pF
capacitance
Drive level (max)
0.8
mW
Copyright
© 2011, Texas Instruments Incorporated
CLOCK CONNECTIONS
17
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