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HMC702LP6CE

v07.0411

14 GHz 16-BIT FRACTIONAL-N PLL

Table 34. Reg 18h Auxiliary Oscillator Register 1

Bit

Type

Name

Default

Description

1:0

r/W

dsmclk_auxclk_insel

0

Selects the input clk for auxclk

0:vcodiv

1:xrefsq or sin

2:refdiv

3:ring oscillator from mono, est 300 MHz to

1 GHz

3:2

r/W

dsmclk_auxclk_modesel

0

0: bypass-no delay

1: pass through w/ delay

2: ring-out constant

3: ring-out seeded/gated

6:4

r/W

dsmclk_auxclk_divsel

2

divider selection auxclk value divby

000

001

010

011

100

101

110

111

1

2

4

6

8

10

12

14

7

r/W

dsmclk_auxclk_sel

0

selects auxclk (if=1) as natural reference clk

input of sigma delta

8

r/W

dsmclk_auxmod_lfsr_en

0

enables 10-bit lfsr inside the delay modulator

(clocked by auxclk or auxclkb)

9

r/W

dsmclk_auxmod_accum_en

0

enables 8-bit accumulator inside the delay

modulator (clocked by auxclk or auxclkb)

11:10

r/W

dsmclk_auxmod_mode

0

delay modulation mode

0: auxmod_lodly_in passthrough

1: accumulator based square-wave

2: lfsr (lo-amp)

3: lfsr (hi-amp)

19:12

r/W

dsmclk_auxmod_fracstep

3

step-size of accumulator (changes square-wave

value once it wraps through 256)

22:20

r/W

dsmclk_auxmod_lodly

0

value of delay-element (when auxmod_mode=0)

or low value used during sq-wave modulation

Table 35. Reg 19h Auxiliary Oscillator Register 2

Bit

Type

Name

Default

Description

2:0

r/W

dsmclk_auxmod_hidly

7

hi value of delay element during sq-wave

modulation

3

r/W

dsmclk_auxmod_clkinv

1

optionally inverts auxclk as used by the

modulator

4

r/W

dsmclk_auxmod_clkwring

9

select LKD ringosc to clock the LFSr